1.1 Hybrid bonding

Recently, 3D packaging has become crucial for high-integration AI/HPC (artificial intelligence/high-performance computing) applications, such as the combination of HBM (high-bandwidth memory) and logic dies, because it minimizes signal delay and maximizes power efficiency through reduced inter-chip distances. In particular, Cu-dielectric hybrid bonding is suitable for implementing ultra-fine pitches less than 10 µm by combining Cu-Cu with SiO₂-SiO₂ or SiCN-SiCN and enables high-bandwidth low-delay connections between chips^[1,2].

The Cu-SiO₂ hybrid process requires annealing at 280–400 °C, which may cause thermal damage to heat-sensitive devices. To address this issue, research on low-temperature bonding at 220 °C or below is being actively conducted^[1]. For successful low-temperature bonding, it is essential to achieve a flat, contamination-free surface and to precisely control the dishing and protrusion of Cu pads at the nanometer level^[3]. However, the CMP process exhibits different removal rates depending on the mechanical and chemical properties of the materials. As shown in Figure 1, soft Cu pads with a nano-indentation hardness of 1–2 GPa have lower abrasion resistance than SiO₂ (4–12 GPa) or SiCN (16–20 GPa) dielectrics, making them highly susceptible to dishing^[4].

Dishing significantly affects the reliability of hybrid bonding. According to Li et al., recessed Cu pads form physical gaps during bonding, as shown in Figure 2, reducing the effective Cu height^[5]. This increases the resistance R in Eq. 1 and the height difference b with the surrounding dielectric, thereby impairing electrical stability.

Furthermore, a study by Le et al. demonstrated that during the final heating stage of the post-annealing process, a maximum peeling stress (σyy) of 680 MPa occurs at the SiCN–SiCN interface under conditions of 300 °C and 5 nm dishing, indicating vulnerability to cracking^[6]. Additionally, according to Lee et al., increased roughness at the bonding interface induces leakage currents. Therefore, achieving nanometer-level planarity is essential not only to suppress vacancy defects but also to ensure stable device operation^[7].

Based on this background, it is important to precisely control the dishing phenomenon at the nanometer level for successful hybrid bonding technology, but it is hard to find a paper reviewed on dishing. So, we will focus on the paper published nowadays, which is about the effect of dishing on hybrid bonding.

Fig. 1. Cu dishing and oxide erosion.

Fig. 2. Formation of physical gaps due to dishing after the CMP process, during SiO₂ and Cu hybrid bonding.

1.2 From TSV Cu CMP to hybrid Cu bonding interfaces

Chemical mechanical polishing has been widely investigated in the context of Cu interconnects and TSV (through-silicon via) interfaces, and these applications significantly contribute to current CMP procedures. In TSV processes, CMP primarily serves to remove overburden Cu and achieve global planarization for subsequent steps. In contrast, hybrid Cu bonding relies directly on the CMP-processed surface as the bonding interface, where nanometer-scale topography, surface chemistry, and defect distribution critically determine bonding yield and reliability. Systematic CMP studies explicitly targeting hybrid Cu bonding interfaces remain limited. However, rather than presenting TSV studies as directly equivalent, this review intentionally reinterprets them as mechanistic analogs that elucidate fundamental CMP behaviors, such as pressure localization, removal rate selectivity, and pattern dependency, that also govern surface evolution in hybrid bonding structures. This distinction is explicitly stated here to avoid conceptual ambiguity. By distinguishing between TSV CMP and hybrid Cu bonding requirements, and by prioritizing bonding-interface-centric discussions in the Introduction, this manuscript highlights perspectives on CMP as a bonding-critical process step. This aligns with the scope of the review while leveraging the CMP literature to build a rigorous and physically grounded understanding of dishing control in hybrid Cu bonding.

1.3 Target application and CMP requirements for hybrid Cu bonding

The target application of the Cu CMP process discussed in this review is Cu/dielectric hybrid bonding, especially Cu/SiO₂ hybrid bonding for advanced 3D heterogeneous integration, particularly for ultra-fine-pitch interconnects used in HPC, AI, and HBM integration. Unlike conventional Cu CMP processes developed for back-end processes or TSV planarization, CMP for hybrid Cu bonding must satisfy a distinct and more stringent set of specifications, as the CMP-processed surface directly serves as the bonding interface^[5,6].

In hybrid Cu bonding applications, the CMP step immediately preceding bonding defines the final surface topography, chemistry, and defect distribution that govern bonding yield, interfacial void formation, and long-term reliability. Typical target specifications include Cu dishing controlled to the sub–5 nm regime, dielectric erosion minimized to avoid oxide roll-off, elimination of fang formation, and ultra-low surface roughness (often <0.3 nm RMS) over both Cu and dielectric regions. These requirements are substantially tighter than those for TSV CMP, where dishing on the order of tens to hundreds of nanometers can be tolerated without directly affecting electrical performance or mechanical integrity. Park et al. reported that reducing surface roughness to a level below the pattern width is critical for process reliability, as evidenced by a dramatic increase in transfer yield from 3% to 99% through optimized planarization^[8].

The distinction between applications is critical. In TSV processes, CMP primarily functions to remove electroplated Cu overburden and achieve global planarization for subsequent metallization or packaging steps. Moderate dishing, dielectric erosion, and local non-uniformity may be acceptable, as the CMP surface does not directly participate in bonding. In contrast, for hybrid Cu bonding, even nanometer-scale topographical deviations translate into interfacial gaps that cannot be fully compensated by Cu atomic diffusion during low-temperature annealing. Consequently, CMP-induced defects become primary reliability-limiting factors rather than secondary process artifacts.

This application-specific context also explains why CMP process optimization strategies differ fundamentally between TSV and hybrid bonding. For TSV CMP, high removal rate and throughput are often prioritized, whereas hybrid bonding CMP demands selective removal rate control, balanced chemical–mechanical interactions, and defect suppression at Cu/dielectric boundaries. Multi-step CMP schemes, selective slurry formulations, and advanced dielectric materials such as SiCN are therefore emphasized in hybrid bonding processes, as they enable simultaneous control of dishing, dielectric erosion, and post-CMP surface integrity^[9].

Throughout this review, the discussion of Cu CMP is intentionally framed around these hybrid bonding–specific requirements. TSV-based CMP studies are referenced primarily to elucidate fundamental mechanisms, such as pressure localization, pattern density effects, and removal rate selectivity, that remain relevant at smaller length scales. However, the evaluation of CMP performance, defect tolerance, and process optimization is consistently benchmarked against the demands of hybrid Cu bonding rather than TSV fabrication. This application-driven perspective ensures that the relevance and impact of the reviewed CMP strategies can be properly assessed within the context of next-generation 3D integration technologies.

1.4 Distinction between dishing metrics in hybrid Cu bonding and TSV CMP

The Cu dishing values reported throughout the CMP literature span a wide range, from sub–3 nm to several tens to hundreds of nanometers. This apparent inconsistency is not contradictory but instead reflects fundamentally different target applications, structural geometries, and evaluation criteria. In the context of this review, it is therefore essential to clearly distinguish between hybrid Cu bonding–relevant dishing values and those originating from TSV Cu CMP processes.

For hybrid Cu bonding, Cu dishing is an interface-critical parameter. Numerous experimental and simulation studies have demonstrated that, although the exact allowable dishing depends on Cu pad size and pitch, Cu dishing must generally be controlled to below approximately 3 nm to achieve high bonding yield under low-temperature annealing conditions. Dishing exceeding this threshold leads to persistent interfacial gaps that cannot be fully eliminated by Cu atomic diffusion, resulting in unbonded regions, increased electrical resistance, and degraded mechanical reliability. Consequently, figures such as Figure 8, which report dishing values on the order of approximately 2 nm, represent CMP conditions that are explicitly optimized for hybrid Cu bonding interfaces and should be interpreted as bonding-qualified results.

In contrast, Cu dishing values in the range of 20–40 nm originate from CMP processes developed for TSV or interposer-related applications^[10,11]. TSV Cu CMP inherently results in larger dishing due to several structural and process-related factors, including large Cu feature sizes, high aspect ratios, significant Cu overburden thickness, and non-uniform pattern density. In TSV applications, CMP primarily serves to remove electroplated Cu overburden and achieve global planarization, and the CMP-processed surface does not directly function as a bonding interface. As a result, dishing values that would be unacceptable for hybrid bonding are often tolerated in TSV processes without compromising device functionality.

The inclusion of TSV-related dishing data in this manuscript is therefore intentional but contextual. Dishing values in the tens of nanometers are presented to illustrate mechanistic trends, such as the influence of over-polishing time, removal rate selectivity, and pattern geometry on dishing evolution. These data should not be interpreted as acceptable targets for hybrid Cu bonding but rather as baseline references that highlight the magnitude of dishing reduction required when transitioning from TSV CMP to bonding-centric CMP processes.

To avoid ambiguity, this manuscript now explicitly differentiates between bonding-acceptable dishing (<3 nm) and process-characterization dishing (≥20 nm) associated with TSV CMP. Figures and discussions reporting larger dishing values are positioned as demonstrating correction strategies, scaling behavior, or removal rate control mechanisms, while hybrid bonding–specific CMP results are clearly identified as meeting nanometer-level dishing requirements. This distinction is particularly important when evaluating multi-step CMP processes^[11], where dishing values observed at intermediate CMP stages may appear large but are subsequently corrected to bonding-compatible levels.

1.5 Organization, Scope, and Review Framework

This review aims to provide a focused, application-driven review of Cu CMP processes relevant to hybrid Cu bonding interfaces rather than surveying all CMP technologies. The Cu CMP processes reviewed in this manuscript are limited to those directly influencing post-CMP surface integrity for Cu/dielectric hybrid bonding, where the CMP-processed surface itself functions as the bonding interface. Accordingly, this review does not aim to cover conventional back-end interconnect CMP or TSV CMP. Instead, TSV-related CMP studies are selectively referenced only where they provide mechanistic insight into dishing evolution, removal rate selectivity, pattern density effects, or defect formation mechanisms that remain relevant at smaller length scales. These studies serve as mechanistic baselines, while the evaluation criteria throughout the manuscript are consistently benchmarked against hybrid bonding requirements.

This review is organized as follows. Section 2 focuses on the mechanisms of Cu dishing and CMP-induced defects, including oxide roll-off and fang formation, with explicit discussion of how these phenomena influence hybrid bonding reliability. Section 3 reviews dishing control strategies, systematically categorized into process-based (slurry chemistry and multi-step CMP), material-based (dielectric selection such as SiCN), and design-based (pattern density, etc.) approaches. Each strategy is discussed with explicit reference to its effectiveness in meeting the nanometer-scale surface requirements of hybrid Cu bonding. Finally, the Conclusions section synthesizes these elements to highlight CMP as a bonding-critical surface engineering step rather than a simple planarization process.

2.1. Causes of Dishing

Dishing is a phenomenon in which concave regions are created during the CMP process because ductile Cu has a higher local MRR (material removal rate) compared to hard dielectrics (e.g., SiO₂, SiCN) due to its lower abrasion resistance and susceptibility to chemical erosion. Roh et al. reported a dishing phenomenon in Cu-filled TSVs (through-silicon vias) with a diameter of 44.3 µm, where the Cu surface was 0.275 µm (275 nm) lower than the surrounding Si substrate after CMP. Figure 3 shows the surface after completing the CMP process on electroplated Cu-filled TSVs^[9]. In TSVs, using solder bumps for Si die stacking, rough polishing and over-polishing result in excessive dishing of approximately 275 nm, compared to the requirement for hybrid bonding applications.

Fig. 3. 3D surface images and the corresponding depth profiles of Cu–filled TSV. Reproduced from Ref. 7 with permission from Springer.

2.2 CMP-induced defects beyond dishing

Cu dishing rarely occurs as an isolated phenomenon. In practical CMP conditions, oxide roll-off and fang formation are frequently generated concurrently and play a decisive role in determining post-CMP surface integrity and subsequent hybrid bonding reliability. Therefore, for a bonding-centric understanding of CMP, these defects are discussed together with dishing rather than treated as secondary effects. Oxide roll-off refers to the localized recession of the dielectric near the Cu–dielectric boundary, as already shown in Figure 1. This phenomenon originates from the local pressure amplification and removal rate selectivity at Cu edges during CMP. Park et al. demonstrated that the intrinsic hardness of Cu films (~2.0 GPa) transitions into composite hardness influenced by the substrate when the polishing depth exceeds 20% of the film thickness. This suggests that the shifting mechanical response of the film-substrate system can further fluctuate the MRR and aggravate dishing during the final stages of CMP^[12]. According to Preston’s equation (Eq. 2), the material removal rate R(x,t) in CMP, which varies with time and position, is proportional to the local pressure and wear coefficient and can be written as^[10]:

where k(x) is the wear coefficient dependent on the material and slurry chemical composition, v(x) is the relative velocity, and p(x,t) is the local pressure distribution.

When Cu dishing develops, even at the nanometer scale, a height gradient forms between the recessed Cu pad and the surrounding dielectric. According to the pressure–gap relationship described in Eq. 3, this topographical non-uniformity locally increases the polishing pressure at the Cu–dielectric boundary, accelerating dielectric erosion.

Integrating the Preston equation (Eq. 3) with time yields the change in surface topography T(x,t).

Here, T and w is the time-dependent function of the deformed pad surface topography, and a reduction in local gap (d = w - T) leads to an increase in the local polishing pressure.

As a result, oxide roll-off progresses simultaneously with Cu dishing, effectively increasing the local recess depth beyond what is captured by average dishing measurements. This behavior is particularly pronounced in fine-pitch patterns, where boundary effects dominate, as previously reported for narrow Cu pad spacing and small pad sizes^[4,11], as shown in Figure 4.

Fig. 4. (a) Cu dishing depth with various Cu pad spaces depends on Cu pad size and (b) dishing size after 150 s of overpolishing depends on Cu pad size^[4,11].

Fang formation is another CMP-induced defect closely linked to dishing and slurry chemistry. During CMP, non-uniform formation and removal of Cu oxide or passivation layers can lead to partial retention or redeposition of Cu reaction products near the Cu–dielectric interface. With increasing over-polishing time, these residual features can evolve into protruding ridge-like structures, commonly referred to as fangs. From a topographical standpoint, fang formation appears to locally counteract Cu dishing; however, it is highly detrimental to hybrid bonding. Fang-induced protrusions generate severe local stress concentrations during pre-bonding contact and post-annealing, increasing the likelihood of dielectric cracking and interfacial delamination. This behavior is consistent with reported numerical analyses showing strong stress amplification at non-uniform Cu/dielectric interfaces during thermal cycling^[6].

The combined presence of dishing, oxide roll-off, and fang formation fundamentally alters the post-CMP surface relevant to hybrid bonding. Even when the average Cu dishing depth is controlled below 5 nm, excessive oxide roll-off can locally increase the effective Cu recess beyond the diffusion capability of Cu atoms during low-temperature annealing, leading to persistent interfacial voids^[5,6]. Conversely, fang formation can cause premature localized Cu–Cu contact, resulting in non-uniform bonding pressure distribution and incomplete bonding in adjacent regions. This explains why CMP processes optimized solely for Cu removal rate or global dishing control often fail to achieve high bonding yield, particularly under low-temperature (<250 °C) hybrid bonding conditions.

From the perspective of hybrid bonding, CMP must therefore be regarded as a bonding-critical surface engineering step, not merely a planarization or Cu removal process. The CMP process preceding hybrid bonding must simultaneously suppress Cu dishing, minimize oxide roll-off, and eliminate fang formation while maintaining ultra-low surface roughness and chemical cleanliness. Achieving this requires holistic optimization of slurry chemistry (oxidizer concentration, corrosion inhibitors, and abrasive selectivity), polishing pad compliance, and multi-step CMP strategies capable of correcting edge-related defects. As demonstrated in recent studies on slurry design and multi-step CMP correction schemes, controlling removal rate between Cu and dielectric is essential not only for dishing mitigation but also for suppressing secondary defects that directly impact bonding reliability^[11,32,35].

In summary, a CMP process that simply removes Cu is insufficient for hybrid bonding applications. Instead, the CMP process completed immediately before bonding must be optimized with consideration of dishing, oxide roll-off, and fang formation, as these defects collectively determine interfacial contact uniformity, Cu diffusion efficiency, and long-term bonding reliability in advanced 3D heterogeneous integration.

The geometric structure of the Cu pad pattern is also a factor determining the magnitude of dishing. According to a study by Ji et al., as shown in Figure 4, expanding the inter-pad spacing from 2 µm to 4 µm increases the dishing depth for the same pad size. Notably, 2 µm pads react more sensitively to spacing changes than 4 µm pads^[4]. When Cu pad spacing was 2 µm and 3 µm, a large dishing depth difference of approximately 8 nm was observed between 2 µm and 4 µm pads, but this difference decreased to a negligible 0.75 nm when the spacing was 4 µm.

Therefore, according to Eq. 3, as the over-polishing time increases, the cumulative material removal at the bottom of the Cu patterns increases, thereby exacerbating the dishing phenomenon^[10]. In particular, dishing deviation was noted as a major variable heavily dependent on the initial electroplated Cu size and the increase in over-polishing time. Liu et al. confirmed that after 150 seconds of over-polishing, 50 µm pads had a dishing depth of 476 nm, while 10 µm pads had 159 nm, indicating that larger pads have a higher rate of dishing increase over time, resulting in a larger average dishing depth^[11]. This result shows significantly larger dishing compared to the 275 nm dishing depth of the 44.3 µm diameter Cu-filled TSV reported by Roh et al.^[9]. This is because Roh et al.'s result involved a W-Cu alloy. Since the hardness of the alloy is higher than that of pure Cu (as reported by Liu et al.^[11]), the dishing depth is expected to be smaller.

The removal rate selectivity that is determined by the slurry composition is another factor influencing dishing. Seo et al. mentioned that raising the oxidizer (H₂O₂) concentration enhances the formation of a protective film on the Cu surface, showing a tendency to reduce dishing^[3]. Nguyen et al. presented results saying that for 100 µm wide Cu lines, the dishing depth was approximately 250 nm at an oxidizer concentration of 7.5% but decreased to about 120 nm at a concentration of 15%^[13].

To control excessive chemical etching and minimize Cu dishing in CMP, adjustment of corrosion inhibitors in the slurry is necessary. In a paper by Zhao et al. regarding CMP using Ru, the concentration of the corrosion inhibitor 5-methylthio-1H-tetrazole (MTT) was adjusted to the 2000 ppm level to optimize the Cu/Ru removal rate selectivity to 1:1.18^[14]. This reduced the average dishing depth in the 100 µm/100 µm region from 960 Å (96 nm) to 490 Å (49 nm), and in the 50 µm/50 µm region from 650 Å (65 nm) to 410 Å (41 nm).

Additionally, Ming et al. reported a reduction in dishing and scratching by changing and controlling the slurry when applying Damascene CMP to the fabrication of IGZO (InGaZnO) transistors used in DRAM technology^[15]. The conventional oxide slurry A, with a high solid content of 15.9%, caused high levels of scratching after CMP and had a high IZO/SiN removal rate selectivity of 10:1, causing IZO dishing. Slurry B, proposed as an alternative, featured a low solid content (0.6%), acidity (pH ~ 2), H₂O₂ oxidizer, and 100 ppm Fe catalyst. It significantly reduced the IZO/SiN removal rate selectivity to 3:1, thereby reducing the dishing value to 16 nm in 100 nm / 100 nm hole patterns. As seen in the effects of the strategies mentioned in Figure 5, the difference in removal rates significantly affects dishing.

Fig. 5. Cu dishing depth reduction by various methods^[13-15].

The uniformity of dishing after the CMP process is influenced by the micro-topography from preceding processes as well. Cho et al. suggested that sidewall scallops generated during DRIE (deep reactive ion etching) for TSV of Figure 6 are a major factor inhibiting the continuity of the Cu seed layer in the subsequent deposition process^[16]. This causes non-uniform Cu filling, leading to reduced uniformity in the CMP process. In addition, if internal voids generated during the Cu filling process exist near the surface, the pressure applied during CMP can cause local collapse of those areas, inducing severe dishing.

Fig. 6. Scallop formation during Bosch DRIE process. Reproduced from Ref. 13 with permission from MDPI.

Vlassak et al.^[10] reported that according to Eq. 4, a reduction in the local gap (d = w - T) increases the local pressure p at the pad-wafer interface, where T(t) and w(t) denote the wafer and deformed pad surface topographies, respectively. This locally increases the material removal rate during CMP, intensifying dishing in certain areas.

Although TSV-based structures have yielded several fundamental insights into Cu dishing, removal rate selectivity, and pattern density effects (Figures 3, 4, and 6), hybrid Cu bonding places fundamentally distinct and substantially more rigorous demands on post-CMP surface integrity.

2.3. Dishing and Bonding Reliability

3.1 CMP Process Optimization

3.1.1 Slurry Improvement

One of the approaches to controlling dishing is optimization of the slurry’s chemical and physical properties. Yao et al. classified and compared slurries by abrasive size and pH, as shown in Table 1^[51]. Slurries with acidic pH and large abrasive particles showed weak protection for recess regions, resulting in relatively severe dishing. In contrast, slurries with neutral pH and small abrasive particles were designed to suppress chemical reactions in recess regions through a synergistic passivation mechanism while selectively allowing mechanical polishing only in protruding regions. The second slurry reduced dishing by 73% at the wafer center, 85% at the middle, and up to 96% at the edge compared to the first slurry.

Table 1. Distribution of slurry^[51]

Category	Slurry 1	Slurry 2
Abrasive particle size	Large	Small
Chemical etching rate	Fast	Slow
pH	Acidic (1-5)	Neutral (6-8)

Furthermore, Yun et al. recently proposed a new process to control dishing by applying a Fenton reaction-based slurry to CMP^[52]. Hydroxyl radicals (-OH) generated by hydrogen peroxide (H₂O₂) and iron ion (Fe²⁺) catalysts form a temporary oxide layer (CuO, Cu₂O) on the Cu surface. This oxide layer forms a relatively uniform film with a hardness of 2.0 GPa, similar to the Cu bulk, working as a temporary protective barrier that prevents excessive corrosion of Cu. Simultaneously, arginine, added to the slurry, acts as a scavenger to chemically etch the oxide layer, while crystalline ZrO₂ abrasives smaller than 20 nm efficiently remove this Cu_xO oxide layer. Thus, polishing proceeds with a precise balance between chemical oxidation, etching, and mechanical removal. Hybrid bonding-specific studies, such as those addressing nanometer-scale dishing tolerance, low-temperature bonding behavior, and bonding yield sensitivity to surface topography, are highlighted as the primary application context. Figure 8 and related discussions directly illustrate CMP optimization strategies developed specifically for hybrid bonding, where achieving a dishing-free or near-zero-dishing surface is essential for reliable Cu–Cu atomic diffusion bonding. In the conventional CMP process shown in Figure 8-(A), dishing of about 13 nm occurred after the first step, and 2.1 nm of dishing remained even after the final second step. Thus, dishing persists even after two CMP passes. In contrast, the Fenton reaction-based CMP process in Figure 8-(B) demonstrated the realization of a near-zero-dishing surface with just a single step.

Fig. 8. Schematic of Cu-film CMP performance under different CMP mechanisms. (A)-(a) Damascene structure prior to CMP; (b) approximately 13 nm dishing after the first-step, chemically dominant CMP; (c) reduction of dishing by a second-step non-selective CMP, resulting in approximately 2.1 nm dishing. (B)-(1) Damascene structure after the Fenton reaction; (2) dishing-free surface achieved by a single-step selective CMP process.

Additionally, Jo et al. reported effective dishing control by introducing a hybrid method combining ionization and atomization of the slurry in the CMP process. In the non-patterned wafer CMP process, the ionized slurry activated the chemical reactivity of the Cu surface layer, improving the material removal rate by 23% for Cu and 39% for SiO₂ compared to conventional methods^[25]. The material removal rate of Cu relative to SiO₂ decreased from 0.346 to 0.306, indicating reduced Cu loss during over-polishing. As a result, in patterned wafers, the Cu dishing depth decreased from 24 nm to 21 nm, and dishing was reduced by 5–28% in the 10–30% over-polishing interval.

Further research by Kang et al. showed that changing the pH and dispersion stability of colloidal silica slurry in the CMP process direct affects dishing control^[53]. When the pH was changed from 4 to 9, the zeta potential increased from -14.5 mV to -50.7 mV, suppressing aggregation. Polishing at pH 9 for 90 minutes reduced surface roughness (Ra) to 0.172 nm, removing the damaged layer and scratches. This suggests that securing slurry stability is necessary for suppressing dishing and defects.

3.1.2. Multi-step CMP Process

Since a single process has fundamental limitations in simultaneously controlling dishing and protrusion, recent attempts have been made to convert protrusion into micro-dishing or correct excessive dishing through multi-step CMP processes.

1) Protrusion control via selective slurry: Under certain process conditions, slurries may polish Cu slightly less than SiO₂, causing protrusion instead of dishing. Khurana et al. added touch-up polishing as a third step using a selective slurry and a hard polishing pad for a short time after the basic two-step CMP process^[33]. This successfully converted 5–10 nm protrusions into 1 nm micro-dishing, securing a uniform recess depth.

2) Correction of excessive dishing by removal rate adjustment: Processes to correct excessive dishing of 100–200 nm caused by copper plating thickness variations in conventional two-step processes have also been researched. Recent research by Liu et al. applied a slurry that polishes dielectric (SiO₂) about three times faster than Cu in the third step after the basic CMP process^[11]. By polishing the dielectric surface faster, the relative height difference between the Cu pad and the dielectric was reduced, successfully decreasing dishing to the 20–40 nm level.

Fig. 9. Schematic diagram of excessive dishing correction: (1) protrusion control with optional slurry, (2) dishing control for correction of excessive washing by adjusting the removal speed.

Jeong et al. used a similar method in the through-glass via (TGV) interposer process^[36]. In the first step of the Cu removal process, surface planarization was primarily achieved by rapidly removing the residual layer; however, dishing of 258 nm occurred in a TGV structure with a via diameter of 100 µm, confirming the need for secondary polishing. In the second step, a slurry with a dielectric (SiO₂) removal rate three times faster than Cu was used to correct the relative height difference. As a result, the dishing depth decreased to 85 nm after the second step correction. This suggests that the multi-step CMP process is effective in correcting dishing problems caused by pad density deviations or local over-etching. This approach may serve as an important alternative for enhancing planarity in high-density TGV and hybrid bonding processes.

3.2. Dishing Mitigation via Material Selection and Design

3.3. Dishing Control via Design

As the CMP process is highly sensitive to Cu pad design, it is necessary to suppress dishing from the design stage. Ji et al., through Atomic Force Microscopy (AFM) analysis, suggested that the distance from the Cu-SiO₂ boundary to the deepest point of dishing is 0.80–0.85 µm for 2 µm wide patterns and 0.5–0.6 µm for 3 µm wide patterns^[4]. That is, dishing deviation is concentrated in the boundary effect zone. Therefore, when designing ultra-fine pads under 1 µm, pad sizes should be designed not to overlap with this characteristic length, and dummy patterns should be inserted in low-pattern-density areas to ensure uniform pattern density. This design strategy mitigates the loading effect, reducing dishing variation and contributing to yield enhancement in high-density circuits.

Moreover, Dubey et al. reported that when the Cu via pitch (1–5 µm) and density (12.6–16%) were varied in the CMP process, a recess deeper than 1 µm occurred in the 3 µm Cu via pitch arrangement^[42]. Also, at a 5 µm pitch, the deviation of the Cu recess depth was the largest. In this case, by uniformly arranging the SiON dielectric, the deviation of the dielectric surface inclination was maintained within 1 nm/µm or less, and the change in AFM surface height within ±5 nm at all pitches. That is, it was shown that the uniform arrangement of the dielectric could ensure the Cu depression behavior in both the central and peripheral portions of the wafer.

Mariappan et al. inserted dummy Cu pads while gradually varying the density from 0% to 25% to ensure uniform Cu pad density, defined as the ratio of the Cu area in a given region relative to a reference area^[31]. This resulted in reducing Cu dishing by approximately twofold and erosion over 7 times by controlling non-uniform polishing pressure during CMP. Additionally, Park et al. applied a soft material with a Young’s modulus of 0.98 GPa and large cylindrical protrusions with a height deviation limited to 6.4 µm for the micro-structured polishing pad^[32]. In this case, dishing was reduced by 69% from 90 nm to 28 nm compared to commercial pads. This confirms that design approaches such as metal pattern density uniformization and pad microstructure optimization also act as influential factors in controlling dishing during the CMP stage.